1 1 1/12/01 supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for the latest product specifications, refer to the supertex website: http://www.supertex.com. for complete liability information on all supertex products, refer to the most curre nt databook or to the legal/disclaimer page on the supertex website. VN0550 bv dss /r ds(on) i d(on) bv dgs (max) (min) to-92 500v 60 ? 150ma VN0550n3 order number / package advanced dmos technology these enhancement-mode (normally-off) transistors utilize a vertical dmos structure and supertex? well-proven silicon-gate manufacturing process. this combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. supertex? vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. package option note: see package outline section for dimensions. n-channel enhancement-mode v ertical dmos fets features ? free from secondary breakdown ? low power drive requirement ? ease of paralleling ? low c iss and fast switching speeds ? excellent thermal stability ? integral source-drain diode ? high input impedance and high gain ? complementary n- and p-channel devices applications ? motor controls ? converters ? amplifiers ? switches ? power supply circuits ? drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) absolute maximum ratings drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55 c to +150 c soldering temperature* 300 c * distance of 1.6 mm from case for 10 seconds. ordering information t o-92 s g d
2 VN0550 switching waveforms and test circuit 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 10v v dd r gen 0v 0v package i d (continuous)* i d (pulsed) power dissipation jc ja i dr *i drm @ t c = 25 c c/w c/w to-92 78ma 250ma 1.0w 125 170 78ma 250ma * i d (continuous) is limited by max rated t j . thermal characteristics symbol parameter min typ max unit conditions bv dss VN0550 500 v v gs = 0v, i d = 1ma v gs(th) gate threshold voltage 2 4 v v gs = v ds , i d = 1ma ? v gs(th) change in v gs(th) with temperature -3.8 -5.0 mv/ cv gs = v ds , i d = 1ma i gss gate body leakage 100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current 10 av gs = 0v, v ds = max rating 1mav gs = 0v, v ds = 0.8 max rating t a = 125 c i d(on) on-state drain current 100 v gs = 5v, v ds = 25v 150 350 v gs = 10v, v ds = 25v r ds(on) 45 v gs = 5v, i d = 50ma 40 60 v gs = 10v, i d = 50ma ? r ds(on) change in r ds(on) with temperature 1 1.7 %/ cv gs = 10v, i d = 50ma g fs forward transconductance 50 100 m v ds = 25v, i d = 50ma c iss input capacitance 45 55 c oss common source output capacitance 8 10 pf c rss reverse transfer capacitance 2 5 t d(on) turn-on delay time 10 t r rise time 15 t d(off) turn-off delay time 10 t f fall time 10 v sd diode forward voltage drop 0.8 v v gs = 0v, i sd = 0.5a t rr reverse recovery time 300 ns v gs = 0v, i sd = 0.5a notes: 1. all d.c. parameters 100% tested at 25 c unless otherwise stated. (pulse test: 300 s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. electrical characteristics (@ 25 c unless otherwise specified) drain-to-source breakdown voltage static drain-to-source on-state resistance ma v gs = 0v, v ds = 25v f = 1 mhz v dd = 25v, i d = 150ma, r gen = 25 ? ns ? ?
3 VN0550 t ypical performance curves
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4 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 ?fax: (408) 222-4895 www.supertex.com 1 1/12/01 ?001 supertex inc. all rights reserved. unauthorized use or reproduction prohibited. VN0550 t ypical performance curves c oss gate drive dynamic characteristics q g (nanocoulombs) v gs (volts) t j ( c) v gs(th) (normalized) v ds (th) and r variation with temperature on-resistance vs. drain current r ds(on) (ohms) bv dss (normalized) t j ( c) transfer characteristics v gs (volts) i d (amperes) capacitance vs. drain-to-source voltage 100 75 50 25 0 c (picofarads) v ds (volts) i d (amperes) bv dss variation with temperature 0102 03040 0246810 0.5 0.4 0.3 0.2 0.1 0 -50 0 50 100 150 1.1 1.0 0.9 100 80 60 40 20 0 1.4 1.2 1.0 0.8 0.6 10 8 6 4 2 0 0.2 0.4 0.6 0.8 1.0 -50 0 50 100 150 50 pf v ds = 40v v ds = 10v 105 pf v (th) @ 1ma v gs = 5v v gs = 10v t = -55 a c v ds = 25v c iss c rss 25 c 150 c 0 0.1 0.2 0.3 0.5 0.4 r ds(on) @ 10v, 50ma f = 1mhz 112 pf 1.8 1.4 1.0 0.6 0.2 0 r ds(on) (normalized)
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